View H27UAG8T2A_38522.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash
16 Gb NAND Flash H27UAG8T2A
www..net
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 0.5 / Jul. 2009 1
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash Document Title 16 Gbit (2048 M x 8 bit) NAND Flash Memory
Revision History
Revisio n No.
0.0 0.1 0.2 Initial Draft. Deleted ULGA PKG Changed 1. ICC2 current: Typ 15mA/ Max 30mA => 20mA/40mA 2. Added AC parameter values for cache operation 1. Corrected Table 10 & Table 11. 5th byte of Device Identifier & Data 2. Changed Figure 31 : Power on Reset 3. Corrected Bad Block Management SLC to MLC Deleted supply voltage for I/O buffer (VCCQ) 1. Corrected 5th cycle command from 34h to 44h at figure28. Read ID operation. 2. Changed tADL. Min. from 200 to 70 at Table 18:AC Timing Characteristics.
History
Draft Date
Jul. 16. 2008 Feb. 25. 2009 Mar. 30. 2009
Remark
Preliminary Preliminary Preliminary
0.3 0.4 0.5
Apr. 24. 2009 Apr. 29. 2009 Jul. 21. 2009
Preliminary Preliminary Preliminary
www..net
Rev 0.5 / Jul. 2009
2
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash
FEATURES SUMMARY
ELECTRONIC SIGNATURE HIGH DENSITY NAND FLASH MEMORIES
- Cost effective solutions for mass storage applications - 1st cycle : Manufacturer Code - 2nd cycle : Device Code - 3rd cycle : Internal chip number, Cell Type, Number of Simultaneously Programmed Pages. - 4th cycle : Page size, Block size, Organization, Spare size - 5th cycle : Multiplane Information - 6th cycle : Technology (Design Rule), EDO, Interface
MULTIPLANE ARCHITECTURE
- Array is split into two independent planes. Parallel operations on both planes are available, halving program, read and erase time.
NAND INTERFACE
- x8 bus width. - Address / Data Multiplexing - Pin-out compatibility for all densities
COPY BACK PROGRAM
- Fast Data Copy without external buffer - Multi-plane copy-back program
CHIP ENABLE DON'T CARE
- Simple interface with microcontroller
SUPPLY VOLTAGE
- 3.3 V device : Vcc = 2.7 V ~ 3.6 V
STATUS REGISTER
- Normal Status Register (Read/Program/Erase)
MEMORY CELL ARRAY
- (4 K + 224) bytes x 128 pages x 4096 blocks
HARDWARE DATA PROTECTION
- Program/Erase locked during Power transitions.
PAGE SIZE
- (4 K + 224 spare) Bytes
DATA RETENTION
- 5,000 Program/Erase cycles (with 12 bit / 528 byte ECC) - 10 years Data Retention
BLOCK SIZE
- (512 K + 28 K spare) Bytes
PAGE READ / PROGRAM
Random access : 60 us (max.) Sequential access : 25 ns (min.) Page program time : 800(TBD) us (typ.) Multi-Plane Program time (2 pages) : 800(TBD) us (typ.)
PACKAGE
- H27UAG8T2ATR : 48-pin TSOP1(12 x 20 x 1.2 mm) - H27UAG8T2ATR (Lead & Halogen free)
FAST BLOCK ERASE
- Block erase time: 2.5ms (typ.) - Multi-Block Erase time (2 blocks) : 2.5ms (typ.)
www..net
CACHE PROGRAM
- Internal (4K + 224) bytes data buffer to improve program throughput
CACHE READ
- Automatic block download without latency time
Rev 0.5 / Jul. 2009
3
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash
1. SUMMARY DESCRIPTION
The H27UAG8T2A is a 2048Mx8bit with spare 116Mx8 bit capacity. The device is offered with 3.3V Vcc Core Power Supply and 3.3V Input-Output Power Supply. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. The device contains 4096 blocks, composed by 128 pages consisting in two NAND structures of 32 series connected Flash cells. Every cell holds two bits. Like all other 4 KB page NAND Flash devices, a program operation allows to download 4,320 bytes of the page into the page register in 60 usec (max), write the 4,320 byte page in typical 800us, and erase one (512K+28k) byte block in 2.5ms (typ). Thanks to multi-plane architecture, it is possible to read 2 pages, or program 2 pages or to erase 2 blocks at a time; the two pages/blocks belong to the two different physical planes of the array. As a consequence, multi-plane architecture increase memory throughput . Data in the page can be read out or input in the internal register at the following speeds, 25nsec per byte. The I/O pins serve as the ports for address and data input / output as well as command input. This interface allows a reduced pin count and easy migration towards different densities, without any rearrangement of footprint. Commands, Data and Addresses are synchronously introduced using CE, WE, ALE and CLE input pin. The on-chip Program/Erase Controller automates all read, program and erase functions including pulse repetition, where required, and internal verification and margining of data. The modify operations can be locked using the WP Input. The output pin R/B (open drain buffer) signals the status of the device during each operation. In a system with multiple memories the R/B pins can be connected all together to provide a global status signal. The chip supports CE don't care function. This function allows the direct download of the code from the NAND Flash memory device by a microcontroller, since the CE transitions do not stop the read operation. The copy-back function allows the optimization of defective blocks management: when a page program operation fails the data can be directly programmed in another page inside the same array section without the time consuming serial data insertion phase; however, source page data download is possible after copyback read, thus bit manipulation prior to program to the target page is allowed. The cache program feature is implemented; it allows data insertion in the cache register while the data register is copied into the flash array. This pipelined program operation improves the program throughput when long files are written inside the memory. The cache program feature is supported also in multi-plane , in order to further increase device performance. The cache read feature is also implemented. This feature allows to dramatically improve read throughput when consecutive pages have to be streamed out. The cache read feature is supported also in multi-plane , in order to further increase device performance. Even the write-intensive systems can take advantage of the H27UAG8T2A extended reliability of 5 K program/erase cycles by providing 12 bit / 512byte ECC (Error Correcting Code) with real time mapping-out algorithm. This device includes also extra Features like OTP/Unique ID area, Read ID2 extension. The H27UAG8T2A is available in the following packages: TSOP48 (12x20)
www..net
1.1 Product List
PART NUMBER H27UAG8T2A ORGANIZATION x8 Vcc RANGE 2.7V ~ 3.6V PACKAGE 48-TSOP1
Rev 0.5 / Jul. 2009
4
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash
VCC
IO7 - IO0 CLE ALE
Data Input / Outputs Command latch enable Address latch enable Chip Enable Read Enable Write Enable Write Protect Ready / Busy Power Supply Ground No Connection
CE WE RE ALE CLE WP
IO0~IO7 R/B
CE RE WE WP R/B Vcc Vss NC
VSS
Figure 1 : Logic Diagram
Table 1 : Signal Names
www..net
Figure 2 : 48-TSOP1 Contact, x8 Device
Rev 0.5 / Jul. 2009
5
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash 1.2 PIN DESCRIPTION
Pin Name IO0 ~ IO7 Description DATA INPUTS/OUTPUTS The IO pins allow to input command, address and data and to output data during read / program operations. The inputs are latched on the rising edge of Write Enable (WE). The I/O buffer float to High-Z when the device is deselected or the outputs are disabled. COMMAND LATCH ENABLE This input activates the latching of the IO inputs inside the Command Register on the Rising edge of Write Enable (WE). ADDRESS LATCH ENABLE This input activates the latching of the IO inputs inside the Address Register on the Rising edge of Write Enable (WE). CHIP ENABLE This input controls the selection of the device. WRITE ENABLE This input acts as clock to latch Command, Address and Data. The IO inputs are latched on the rise edge of WE. READ ENABLE The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one. WRITE PROTECT The WP pin, when Low, provides an Hardware protection against undesired modify (program / erase) operations. READY BUSY The Ready/Busy output is an Open Drain pin that signals the state of the memory. SUPPLY VOLTAGE The Vcc supplies the power for all the operations (Read, Write, Erase). GROUND NO CONNECTION
CLE
ALE CE WE
RE
WP R/B Vcc Vss NC
Table 2 : Pin Description
NOTE :
www..net
1. A 0.1uF capacitor should be connected between the Vcc Supply Voltage pin and the Vss Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations.
Rev 0.5 / Jul. 2009
6
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash
1 Page = (4K+224) Bytes 0 Plane 1 Plane 1 Block = (4K+224) Bytes x 128 pages = (512K+28K) Bytes 1 Device = (512K+28K)Byte x 4096 Block = 16 Gbit
0 2048 Blocks per Plane 4096 Blocks per device 2 . . . 4092 4094
1 3 . . . 4093 4095
I/O0 ~ 7 Page Buffer 4K Bytes 224 Bytes
Figure 3 : Array Organization
IO0 1st Cycle 2nd Cycle 3rd Cycle 4th Cycle 5th Cycle A0 A8 A13 A21 A29
IO1 A1 A9 A14 A22 A30
IO2 A2 A10 A15 A23 A31
IO3 A3 A11 A16 A24 L(1)
IO4 A4 A12 A17 A25 L(1)
IO5 A5 L(1) A18 A26 L(1)
IO6 A6 L(1) A19 A27 L(1)
IO7 A7 L(1) A20 A28 L(1)
Table 3 : Address Cycle Map
NOTE:
www..net
1. L must be set to Low. 2. the device ignores any additional input of address cycles than required 3. Row address consists of page address (A13-A19) & Plane address (A20) & Block Address (A21 - the last address)
Rev 0.5 / Jul. 2009
7
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash
FUNCTION
PAGE READ MULTI-PLANE READ MULTI-PLANE CACHE READ START SINGLE/MULTI PLANE CACHE READ SINGLE/MULTI PLANE CACHE READ END RANDOM DATA OUTPUT PAGE PROGRAM (START) /CACHE PROGRAM (END) RANDOM DATA INPUT BLOCK ERASE READ FOR COPY-BACK COPY BACK PROGRAM CACHE PROGRAM (START) READ STATUS REGISTER MULTI-PLANE PAGE PROGRAM / MULTI-PLANE CACHE PROGRAM (END) MULTI-PLANE BLOCK ERASE MULTI-PLANE READ FOR COPY BACK MULTI-PLANE COPY BACK PROGRAM MULTI-PLANE CACHE PROGRAM (START) MULTI-PLANE DATA OUTPUT MULTI-PLANE READ STATUS REGISTER READ ID RESET
1st
00h 60h 60h 31h 3Fh 05h 80h 85h 60h 00h 85h 80h 70h 80h 60h 60h 85h 80h 00h F1h 90h FFh
2nd
30h 60h 60h E0h 10h D0h 35h 10h 15h 11h 60h 60h 11h 11h 05h -
3rd
30h 33h 81h D0h 35h 81h 81h E0h -
4th
10h 10h 15h -
Acceptable Command During Busy
YES
YES YES
Table 4 : Command Set
CLE H L H
www..net
ALE L H L H L L X X X X X
CE L L L L L L X X X X H
WE Rising Rising Rising Rising Rising H H X X X X
RE H H H H H Falling H X X X X
WP X X H H H X X H H L 0 V / Vcc Read Mode Write Mode Data Input Data Output
MODE Command Input Address Input (5 cycles) Command Input Address Input (5 cycles)
L L L
X X X X X
During Read (Busy) During Program (Busy) During Erase (Busy) Write Protect Stand By
NOTE : With the CE don't care option CE high during latency time does not stop the read operation
Table 5 : Mode Selection
Rev 0.5 / Jul. 2009
8
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash
1. BUS OPERATION
There are six standard bus operations that control the device. These are Command Input, Address Input, Data Input, Data Output, Write Protect, and Standby. Typically glitches less than 5ns on Write Enable and Read Enable are ignored by the memory and do not affect bus operations.
2.1 Command Input
Command Input bus operation is used to give a command to the memory device. Command are accepted with Chip Enable low, Command Latch Enable High, Address Latch Enable low and Read Enable High and latched on the rising edge of Write Enable. Moreover, for commands that start a modifying operation (write/erase) the Write Protect pin must be high. See Figure 5 and Table 18 for details of the timings requirements. Command codes are always applied on IO<7:0>, disregarding the bus configuration.
2.2 Address Input
Address Input bus operation allows the insertion of the memory address. Five cycles are required to input the addresses for the 16 G bit devices. Addresses are accepted with Chip Enable low, Address Latch Enable High, Command Latch Enable low and Read Enable high and latched on the rising edge of Write Enable. Moreover for commands that starts a modify operation (write/erase) the Write Protect pin must be high. See Figure 6 and Table 18 for details of the timings requirements. Addresses are always applied on IO(7:0), disregarding the bus configuration. In addition, addresses over the addressable space are disregarded even if the user sets them during command insertion.
2.3 Data Input
Data Input bus operation allows to feed to the device the data to be programmed. The data insertion is serially and timed by the Write Enable cycles. Data are accepted only with Chip Enable low, Address Latch Enable low, Command Latch Enable low, Read Enable High, and Write Protect High and latched on the rising edge of Write Enable. See Figure 7 and Table 18 for details of the timings requirements.
2.4 Data Output
Data Output bus operation allows to read data from the memory array and to check the status register content, the lock status and the ID data. Data can be serially shifted out toggling the Read Enable pin with Chip Enable low, Write Enable High, Address Latch Enable low, and Command Latch Enable low. See figures 8, 9, 10,11, 12, 13, 14 and Table 18 for details of the timings requirements.
www..net
2.5 Write Protect
Hardware Write Protection is activated when the Write Protect pin is low. In this condition modify operation do not start and the content of the memory is not altered. Write Protect pin is not latched by Write Enable to ensure the protection even during the power up phases.
2.6 Standby
In Standby mode the device is deselected, outputs are disabled and Power Consumption is reduced. Stand-by is obtained holding CE pin high at least for 10us.
Rev 0.5 / Jul. 2009
9
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash
3. DEVICE OPERATION
3.1 Page Read
Upon initial device power up, the device defaults to page read mode. This operation is also initialized by 00 h to the command register along with followed by five address input cycles. In consecutive read operations, 00h command is needed for the following page read operations. Two types of operations are available: random read, serial page read. The random read mode is enabled when the page address is changed. The 4,320 bytes of data within the selected page are transferred to the data registers in less than 60us (tR). The system controller may detect the completion of this data transfer by either checking the R/B pin level, or issuing the Read Status Register commands (70h or F1h) and monitoring IO<6> (ready/busy) through RE toggling. In the latter case, the device will keep on outputting the Read Status until the command 00h is issued . Once the data in a page is loaded into the data registers, they may be read out by sequentially pulsing RE (every 25nsec) The repetitive high to low transitions of the RE clock make the device output the data starting from the selected column address up to the last column address. The device may output random data in a page instead of the consecutive sequential data by writing random data output command. The column address of next data may be changed to the address which follows random data output command. Random data output can be operated multiple times regardless of how many times it is done in a page.
3.2 Multi Plane Read
Multi-Plane Page Read is an extension of Page Read, for a single plane with 4,320 byte page registers. Since the device is equipped with two memory planes, activating the two sets of 4,320 byte page resisters enables a random read of two pages. Multi-Plane Page Read is initiated by repeating command 60h followed by three address cycles twice. In this case only same page of same block can be selected from each plane, as shown in Figure 14. After Read Confirm command (30h) the 8,640 bytes of data within the selected two pages are transferred to the data registers in less than 60us (tR). The system controller may detect the completion of this data transfer by either checking the R/B pin level, or issuing the Read Status Register commands (70h or F1h) and monitoring IO<6> (ready/busy) through RE toggling. In the latter case, the device will keep on outputting the Read Status until the command 00h is issued . Once the data is loaded into the data registers, the data output of first plane can be read out by issuing command 00h with Five Address Cycles (A20=0), command 05h with two column address and finally E0h. The data output of second plane can be read out using the identical command sequences (but with A20=1). Grey area : a) the device allows to revert the order of the two pages at all times (first read from plane 1 (A20=1) and then from plane0 (A20=0). b) Multi-Plane Page Read is allowed also in the blocks which have NOT been programmed with Multi-Plane Page Program.
www..net
Rev 0.5 / Jul. 2009
10
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash 3.3 Page Program
The device is programmed by page. The number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed 1 times. The addressing should be done in sequential order in a block. A page program cycle consists of a serial data loading period in which up to 4,320 bytes of data may be loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. The serial data loading period begins by inputting the Serial Data Input command (80h), followed by the five cycle address inputs and then serial data. The words other than those to be programmed do not need to be loaded. The device supports random data input in a page. The column address of next data, which will be entered, may be changed to the address which follows random data input command (85h). Random data input may be operated multiple times regardless of how many times it is done in a page. The Page Program confirm command (10h) initiates the programming process. Writing 10h alone without previously entering the serial data will initiate the programming process anyway. The internal write state controller automatically executes the algorithms and timings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command may be entered to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit I/O<6> (busy/ready bit) of the Status Register (70h or F1h). Only the Read Status command and Reset command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit I/O<0> (pass/fail) may be checked. The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status command mode until another valid command is written to the command register. Figure 15 details the sequence. NOTE : the device support program operation with 2kByte data to offer the backward compatibility to the controller which uses the Nand with 2Kbyte page.
3.4 Multi Plane Program
Device supports multiple-plane program: it is possible to program in parallel 2 pages, one per each plane. Page and block address for the two pages must be the same . A multiple plane program cycle consists of a double serial data loading period in which up to 8,640bytes of data may be loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. The serial data loading period begins by inputting the Serial Data Input command (80h), followed by the five cycle address inputs and then serial data for the 1st page. Address for this page must be within 1st plane (A<20>=0). The data of 1st page other than those to be programmed do not need to be loaded. The device supports random data input exactly like page program operation. The Dummy Page Program Confirm command (11h) stops 1st page data input and the device becomes busy for a short time (tDBSY). Once it has become ready again, 81h command must be issued, followed by 2nd page address (5 cycles) and its serial data input. Address for this page must be within 2nd plane (A<20>=1);the data of 2nd page other than those to be programmed do not need to be loaded. Program Confirm command (10h) initiates parallel programming of both pages . User can check operation status by R/B pin or read status register commands (70h or F1h). If user opts for 70h, Status register read will provide a "global" information about the operation in the two planes (IO<6>= ready / busy, IO<0> = pass / fail) If user opts for F1h, Status register read will provide information about the operation in each of the two planes (IO<0> : Global pass/fail, IO<1>: Plane0 pass/fail, IO<2>: Plane1 pass/fail). Please note that only Reset (FFh) or Status register commands (70h / F1h) can be issued during Dummy Busy time (tDBSY); in the latter case please refer to Status register command section for further information. Multi-plane program sequence is described in Figure 16. Grey area : a) Please note that page and block address for the pages in the two planes must be the same. If the user fails to do so the device will program the data in location based on the page and block address of the page issued during the sequence 81h - 10h. b) plane order in the command sequence can be swapped; in other words, user may input first the data of the page in plane 1 (A20=1) and then the data of the corresponding page in plane 0 (A20=0)
www..net
Rev 0.5 / Jul. 2009
11
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash 3.5 Block Erase
The Erase operation is done on a block basis. Block address loading is accomplished in two cycles initiated by an Erase Setup command (60h). Only addresses A20 to A32 are valid while A13 to A19 are ignored. The Erase Confirm command (D0h) following the block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions. At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase verify. Once the erase process starts, the Read Status Register command may be entered to read the status register. The system controller can detect the completion of an erase by monitoring the R/B output, or the Status bit I/O<6> (ready/busy) of the Status Register (commands 70h or F1h). Only the Read Status command and Reset command are valid while erasing is in progress. When the erase operation is completed, the Write Status Bit I/O<0> (pass/fail)) may be checked. Figure 18 details the sequence.
3.6 Multi Plane Erase.
Multiple plane erase, allows parallel erase of two block, one per each memory plane. Block erase setup command (60h) must be repeated two times, each time followed by 1st block and 2nd block address respectively (3 cycles each). As for block erase, D0h command makes embedded operation start. Multi plane erase does not need any Dummy Busy Time between 1st and 2nd block address insertion. Block address for the two blocks must be the same User can check operation status by R/B pin or read status register commands (70h or F1h). If user opts for 70h, Status register read will provide a "global" information about the operation in the two planes (IO<6>= ready / busy, IO<0> = pass / fail) If user opts for F1h, Status register read will provide information about the operation in each of the two planes (IO<0> : Global pass/fail, IO<1>: Plane0 pass/fail, IO<2>: Plane1 pass/fail) Multi-plane erase sequence is described in Figure 19. Grey area : a) Please note that the block address in the two planes must be the same. If the user fails to do so the device will erase the data in location based on the block address issued last (during the sequence 60h - D0h). b) plane order in the command sequence can be swapped; in other words, sequences such as 60h 60h D0h Or 60h 60h D0h are both accepted .
3.7 Copy-Back Program
Copy-Back program with Read for Copy-Back is configured to quickly and efficiently rewrite data stored in one page without data reloading when the bit error is not in data stored. Since the time-consuming re-loading cycles are removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of the block also needs to be copied to the newly assigned free block. Copy-Back operation is a sequential execution of Read for Copy-Back and of copy-back program with the destination page address. A read operation with "35h" command and the address of the source page moves the whole 4,320-byte data into the internal data buffer. A bit error is checked by sequential reading the data output. In the case where there is no bit error, the data do not need to be reloaded. Therefore Copy-Back program operation is initiated by issuing Page-Copy Data-Input command (85h) with destination page address. Actual programming operation begins after Program Confirm command (10h) is issued. Once the program process starts, the Read Status Register command (70h) may be entered to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit I/O<6> of the Status Register (commands 70h or F1h) . When the Copy-Back Program is complete, the Write Status Bit(I/ O<0>) may be checked (Figure 20 & Figure 21). The command register remains in Read Status command mode until another valid command is written to the command register. During copy-back program, data modification is possible using random data input command (85h) as shown in. Copy-Back is allowed only within the same memory plane . NOTE : the device support copy back program operation with 2kByte data to offer the backward compatibility to the controller which uses the Nand with 2Kbyte page.
www..net
Rev 0.5 / Jul. 2009
12
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash 3.8 Multi-Plane Copy-Back Program
Two-Plane Copy-Back Program is an extension of Copy-Back Program for a single plane with 4,320 byte page registers. Since the device is equipped with two memory planes, activating the two sets of 4,320 byte page registers enables a simultaneous programming of two pages. The first step for Multi-Plane Copy Back is to perform Multi-plane read for copyback, by repeating command 60h followed by three address cycles twice. In this case only the same page of same block can be selected from each plane. After Read Confirm command (35h) the 8,640 bytes of data within the selected two pages are transferred to the data registers in less than 60us (tR). The system controller may detect the completion of this data transfer by either checking the R/B pin level, or issuing the Read Status Register commands (70h or F1h) and monitoring IO<6> (ready/busy) through RE toggling. In the latter case, the device will keep on outputting the Read Status until another valid command is written to the command register. Once the data is loaded into the data registers, the data output of first plane can be read out by issuing command 00h with Five Address Cycles (with A20=0), command 05h with two column address and finally E0h. The data output of second plane can be read out using the identical command sequences (this time with A20=1). The sequence 60h-60h-35h is allowed also in the blocks which have NOT been programmed with Multi-Plane Page Program. In the case where there is no bit error, the data do not need to be reloaded. The second step for Multi-Plane copy back is to perform Multi-plane copyback program.The operation is initiated by issuing Page-Copy Data-Input command (85h) followed by the five cycle address cycles for destination page in the first plane. Address for this page must be within 1st plane (A<20>=0). The device supports random data input exactly as the page program operation. The Dummy Page Program Confirm command (11h) stops 1st page data input and the device becomes busy for a short time (tDBSY). Once it has become ready again, 81h command must be issued, followed by 2nd page address (5 cycles) . Address for this page must be within 2nd plane (A<20>=1). Again, random data input is allowed during this phase Program Confirm command (10h) initiates the parallel programming of both pages. User can check operation status by R/B pin or read status register commands (70h or F1h). If user opts for 70h, Status register read will provide a "global" information about the operation in the two planes (IO<6>= ready / busy, IO<0> = pass / fail) If user opts for F1h, Status register read will provide information about the operation in each of the two planes (IO<0> : Global pass/fail, IO<1>: Plane0 pass/fail, IO<2>: Plane1 pass/fail) Status register commands can be issued during Dummy Busy time (tDBSY); Please refer to Status register command section for further information. Copy-Back is allowed only within the same memory plane . Figure 22 describes the command sequence for the multi-plane copy-back operation; it refers to controllers which can handle 8k bytes of data : in this case the copy back program sequence 85h is issued after finishing random data output of the source pages is complete. NOTE : the device support copy-back program operation with 4kByte data to offer the backward compatibility to the controller which uses the Nand with 2Kbyte page. Grey area : a) Multi-Plane Page Read for copy-back is allowed also in the blocks which have NOT been programmed with Multi-Plane Page Program. b) during the copy-back program , page and block address for the pages in the two planes must be the same. If the user fails to do so the device will program the data in location based on the page and block address of the page issued during the sequence 81h - 10h. c) plane order in the command sequence can be swapped; in other words, user may input first the page in plane 1 (A20=1) and then the the corresponding page in plane 0 (A20=0). This is allowed both during Multi-Plane Page Read for copy-back and Multi-plane copy back program sequences. d) any command between 11h and 81h is prohibited except 70h, F1h and FFh
www..net
Rev 0.5 / Jul. 2009
13
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash 3.9 Cache Read
Cache Read is an extension of Page Read,which is available only within a block. Since the device has one cache register, serial data output may be executed while data in the memory is read into cache register, Cache Read is initiated by the page read sequence (00-30h). After random access to the first page is complete (R/B returned to high), 31h command can be latched into the command register. At this time, data of the first page is transferred from the data register to the cache register, while device goes busy for short time (tCBSYR) At the end of this phase cache register data can be output by toggling RE while the next page is read from the memory array into data register. Subsequent pages are read by issuing additional 31h command sequences. If serial data output time of one page exceeds random access time (tR), the random access time of the next page is hidden by data downloading of the previous page. On the other hand, if 31h is issued prior to complete the random access to the next page, the device will stay busy as long as needed to complete random access to this page, transfer its contents into the cache register, and trigger the random access to the following page. To terminate cache read, 3Fh command should be issued. This command transfer data from data register to the cache register without issuing next page read. During the Cache Read Operation, device doesn't allow any other command except of 31h and 3Fh or Read SR. To carry out other operations Cache read must be ended either by 3Fh command or device must be reset by issuing FFh. Read Status command (70h) may be issued to check the status of the different registers, and the busy/ready status of the cached read operations. More in detail: a) the Cache-Busy status bit I/O<6> indicates when the cache register is ready to output new data. b) the status bit I/O<5> can be used to determine when the cell reading of the current data register contents is complete See Table 8 and Figure 24 for more details.
3.10 Multi Plane Cache Read
Multi-Plane Cache Read is an extension of Cache Read, and is available only within two paired blocks belonging to the two planes. Since the device has one cache register in each plane, serial data output from the data registers of the two planes may be executed while data in the memory is read into the cache registers, Multi-Plane Cache Read is initiated by the following sequence : a) 60h followed by three address cycles of the page of the first plane b) 60h followed the three address cycles of the corresponding page of the second plane c) 33h (confirm cycle) After random access to the first pages is complete (R/B returned to high), 31h command can be latched into the command register. At this time, data of the first pages is transferred from the data registers to the cache registers, while device goes busy for short time (tCBSYR) .
www..net
At the end of this phase cache register data of the first page can be output by issuing the following sequence : a) 00h followed by the five address cycles related to this page b) 05h followed by two address cycles related to the column address to start the read out c) E0h, followed by toggling RE Similarly the cache register data of the second page can be output by issuing the following sequence : d) 00h followed by the five address cycles related to this page e) 05h followed by two address cycles related to the column address to start the read out f) E0h, followed by toggling RE
Subsequent pages are read from the memory array into the data registers by issuing additional 31h command sequences. If serial data output time of the two pages exceeds random access time (tR), the random access time of the next pages is hidden by data downloading of the previous pages. On the other hand, if 31h is issued prior to complete the random access to the next pages, the device will stay busy as long as needed to complete random access to these pages, transfer their contents into the cache register, and trigger the random access to the following pages.
Rev 0.5 / Jul. 2009
14
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash
To terminate cache read, 3Fh command should be issued. This command transfer data from data registers to the cache registers without issuing next page read. During the Cache Read Operation, device doesn't allow any other command except of 31h and 3Fh or Read SR. To carry out other operations Cache read must be ended either by 3Fh command or device must be reset by issuing FFh. User can check operation status by R/B pin or read status register commands (70h or F1h). More in detail: a) I/O<6> indicates when both cache registers are ready to output new data. b) I/O<5> indicates when the cell reading of the current data registers is complete See Table 8 and Table 9 for more details Figure 25 shows the command sequence for the multi-plane cache read operation. Grey area : a) Please note that page and block address for the pages in the two planes must be the same. If the user fails to do so the device will read the data in location based on the page and block address of the last page issued during the sequence 60h - 60h - 33h. b) plane order in the command sequence 60h - 60h - 33h can be swapped; in other words, user may input first the address of the page in plane 1 (A20=1) and then the data of the corresponding page in plane 0 (A20=0). c) plane order in the command sequence for data readout (00h - 05h - E0h) can be swapped. in other words, user may output first the address of the page in plane 1 (A20=1) and then the data of the corresponding page in plane 0 (A20=0).
3.11 Cache program
Cache Program is an extension of the standard page program which is executed with two 4,320 bytes registers, the data and the cache register. In short, the cache program allows data insertion for one page while program of another page is under execution. Cache program is available only within a block After the serial data input command (80h) is loaded to the command register, followed by 5 cycles of address, a full or partial page of data is latched into the cache register. Once the cache write command (15h) is loaded to the command register, the data in the cache register is transferred into the data register for cell programming. At this time the device remains in Busy state For a short time (tCBSYW). After all data of the cache register are transferred into the data register, the device returns to the Ready state, and allows loading the next data into the cache register through another cache program command sequence (80h-15h). The Busy time following the first sequence 80h - 15h equals the time needed to transfer the data of cache register to the data register. Cell programming of the data of data register and loading of the next data into the cache register is consequently processed through a pipeline model. In case of any subsequent sequence 80h - 15h, transfer from the cache register to the data register is held off until cell programming of current data register contents is complete; till this moment the device will stay in a busy state (tCBSYW usec). Read Status command (70h) may be issued to check the status of the different registers, and the pass/fail status of the cached program operations. More in detail: a) the Cache-Busy status bit I/O<6> indicates when the cache register is ready to accept new data. b) the status bit I/O<5> can be used to determine when the cell programming of the current data register contents is complete c) the cache program error bit I/O<1> can be used to identify if the previous page (page N-1) has been successfully programmed or not in cache program operation. The latter can be polled upon I/O<6> status bit changing to "1" . d) the error bit I/O<0> is used to identify if any error has been detected by the program / erase controller while programming page N. The latter can be polled upon I/O<5> status bit changing to "1". I/O<1> may be read together with I/O<0> . If the system monitors the progress of the operation only with R/B, the last page of the target program sequence must be programmed with Page Program Confirm command (10h). If the Cache Program command (15h) is used instead, the status bit I/O<5> must be polled to find out if the last programming is finished before starting any other operation. See Table 8 and Figure 26 for more details.
Rev 0.5 / Jul. 2009 15
www..net
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash 3.12 Multi Plane Cache program
The device supports multi-plane cache program, which enables high program throughput by programming two pages in parallel while exploiting the data and cache registers of both planes to implement cache. The command sequence can be summarized as follows : a) Serial Data Input command (80h), followed by the five cycle address inputs and then serial data for the 1st page. Address for this page must be within 1st plane (A<20>=0). The data of 1st page other than those to be programmed do not need to be loaded. The device supports random data input exactly like page program operation. b) The Dummy Page Program Confirm command (11h) stops 1st page data input and the device becomes busy for a short time (tDBSY). c) Once device returns to ready again, 81h command must be issued, followed by 2nd page address (5 cycles) and its serial data input. Address for this page must be within 2nd plane (A<20>=1). The data of 2nd page other than those to be programmed do not need to be loaded. d) Cache Program confirm command (15h) Once the cache write command (15h) is loaded to the command register, the data in the cache registers is transferred into the data registers for cell programming. At this time the device remains in Busy state for a short time (tCBSYW). After all data of the cache registers are transferred into the data registers, the device returns to the Ready state, and allows loading the next data into the cache register through another cache program command sequence. The sequence 80h-...- 11h...-...81h...-...15h can be iterated, and any new time the device will be busy for a for the tCBSYW time needed to complete cell programming of current data registers contents, and transfer from cache registers can be allowed. The sequence to end multi-plane cache program is 80h-...- 11h...-...81h...-...10h . Figure 27 shows the command sequence for the multi plane cache program operation. Multi-plane Cache program is available only within two paired blocks belonging to the two planes.. Grey area : a) page and block address for the pages in the two planes must be the same. If the user fails to do so the device will program the data in location based on the page and block address of the page issued during the sequence 81h - 15h (or 81h - 10h) b) plane order in the command sequence can be swapped; in other words, user may input first the data of the page in plane 1 (A20=1) and then the data of the corresponding page in plane 0 (A20=0) User can check operation status by R/B pin or read status register commands (70h or F1h). If user opts for 70h, Status register read will provide a "global" information about the operation in the two planes . More in detail: a) I/O<6> indicates when both cache registers are ready to accept new data. b) I/O<5> indicates when the cell programming of the current data registers is complete c) I/O<1> identifies if the previous pages in both planes (pages N-1) have been successfully programmed or not. The latter can be polled upon I/O<6> status bit changing to "1" . d) I/O<0> identifies if any error has been detected by the program / erase controller while programming the two pages N. The latter can be polled upon I/O<5> status bit changing to "1".
www..net
See Table 8 for more details. If user opts for F1h, Status register read will provide information about the operation in each of the two planes . More in detail : a) I/O<6> indicates when both cache registers are ready to accept new data. b) I/O<5> indicates when the cell programming of the current data registers is complete c) I/O<0> identifies if any error has been detected by the program / erase controller while programming the two pages N. The latter can be polled upon I/O<5> status bit changing to "1". d) I/O<1> is the pass/fail flag for current page (N) programming in plane0 e) I/O<2> is the pass/fail flag for current page (N) programming in plane1 Both d) and e) can be polled upon I/O<5> status bit changing to "1".
Rev 0.5 / Jul. 2009
16
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash
f) I/O<3> is the pass/fail flag for the previous page (N-1) programming in plane0 g) I/O<2> is the pass/fail flag for the previous page (N-1) programming in plane1 Both f) and g) can be polled upon I/O<6> status bit changing to "1". If the system monitors the progress of the operation only with R/B, the last pages of the target program sequence must be programmed with Page Program Confirm command (10h). If the Cache Program command (15h) is used instead, the status bit I/O<5> must be polled to find out if the last programming is finished before starting any other operation. Refer to the Read Status Register section for further information. See Table 9 for more details
3.13 Read Status Register
The device contains a Status Register which may be read to find out whether read, program or erase operation is completed, and whether the program or erase operation is completed successfully. After writing 70h or F1h (multi-plane read status command) command to the command register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. The command register remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read cycle, the read command (00h) should be given before starting read cycles. User can check operation through two different read status register commands (70h or F1h). If user opts for 70h, Status register read will provide a "global" information about the operation in the device ; more precisely, during a multi-plane each status register bit of Status register read command (70h) provides a combined information (OR or AND) of the events occurring in the two planes . The table below summarizes the logic function for each 70h Status register bit in a multi-plane operation : Status Register Bit IO<0> IO<1> IO<5> IO<6> Table 6 below describes the meaning of each Status Register bit IO
www..net
Logic combination between planes OR OR AND AND
Program Pass / Fail NA NA NA NA NA
Erase Pass / Fail NA NA NA NA NA
Read NA NA NA NA NA NA
Cache Read NA NA NA NA NA Ready/Busy Ready / Busy Write Protect
Cache Program Pass / Fail Pass / Fail NA NA NA Ready/Busy Ready / Busy
Coding 70h N page : Pass : `0' Fail : `1' N -1 page : Pass : `0' Fail : `1' Ready/Busy Busy: '0' Ready: `1' Data Cache Ready / Busy Busy : `0' Ready : `1'
0 1 2 3 4 5 6 7
Ready / Busy Ready / Busy Ready / Busy Write Protect Write Protect Write Protect
Write Protect Protected : `0', Not Protected : `1'
Table 6 : Normal (70h) Read Status Register Coding
Rev 0.5 / Jul. 2009 17
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash
NOTE : I/Os defined as NA are recommended to be masked out when Read Status is being executed. If user opts for F1h, Status register read will provide additional information about multi-plane operations, as it allows to check the outcome of the operation in each of the two planes . Table 7 describes the meaning of each Status Register bit during "non cached" multiplane operations, while Table 8 refers to the Cached multi-plane ones IO 0 1 2 3 4 5 6 7 Multi-plane Page Program Pass / Fail Pass / Fail Pass / Fail NA NA NA Ready / Busy Write Protect Multi-plane Block Erase Pass / Fail Pass / Fail Pass / Fail NA NA NA Ready / Busy Write Protect Multi-plane Read NA NA NA NA NA NA Ready / Busy Write Protect Coding : F1h Pass : `0' Fail : `1' Plane0 : Pass : `0' Fail : `1' Plane1 : Pass : `0' Fail : `1' Data Cache Ready / Busy Busy : `0' Ready : `1' Protected : `0' Not Protected : `1'
Table 7 : Multi-plane Read Status Register Coding (non cached operations)
NOTE : I/Os defined as NA are recommended to be masked out when Read Status is being executed.
IO 0 1 2 3
www..net
Multi-plane Page Program Pass / Fail Pass / Fail Pass / Fail Pass / Fail Pass / Fail Ready / Busy Ready / Busy Write Protect
Multi-plane Block Erase NA NA NA NA NA Ready / Busy Ready / Busy Write Protect
Coding : F1h Pass : `0' Fail : `1' N page / Plane 0 Pass : `0' Fail : `1' N page / Plane 1 Pass : `0' Fail : `1' N-1 page / Plane 0 Pass : `0' Fail : `1' N-1 page / Plane 1 Pass : `0' Fail : `1' Ready/Busy Busy : `0' Ready : `1' Data Cache Ready / Busy Busy : `0' Ready : `1' Protected : `0' Not Protected : `1'
4 5 6 7
Table 8 : Multi-plane Read Status Register Coding (cached operations)
NOTE : I/Os defined as NA are recommended to be masked out when Read Status is being executed.
Rev 0.5 / Jul. 2009
18
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash 3.14 Read ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Six read cycles sequentially output the manufacturer code (Numonyx), the device code and 3rd, 4th, 5th, 6th cycle ID, respectively. The command register remains in Read ID mode until further commands are issued to it. Figure 28 shows the operation sequence, while Table 9, Table 10 and Table 11 explain the byte meaning. Parameter Device Identifier Byte 1st 2nd 3rd 4th 5th 6th Symbol Description Manufacturer Code Device Identifier Internal chip number, cell Type, Number of Simultaneously Programmed Pages, Interleaved Program, Write Cache. Page size, Block size, Redundant area size Plane Number, ECC Level Technology (Design Rule), EDO, Interface
Table 9 : Device Identifier Coding
3rd cycle
Description 1 2 4 Reserved 2 Level Cell 4 Level Cell 8 Level Cell 16 Level Cell 1 2 4 8 Not Supported Supported Not Supported Supported
I/O 7 I/O 6 I/O 5 I/O 4 I/O 3 I/O 2 I/O 1 I/O 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Internal Chip Number
Cell Type
Number of Simultaneously Programmed Pages
www..net
Interleaved Program between Multiple dice Write Cache
Table 10 : 3rd, 4th, 5th and 6th byte of Device Identifier
Rev 0.5 / Jul. 2009
19
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash
4th cycle Page Size
Description 2 KB 4 KB 8 KB Reserved 128 KB 256 KB 512 KB 768 KB 1 MB Reserved Reserved Reserved 128 B 224 B Reserved Reserved Reserved Reserved Reserved Reserved Description 1 2 4 8 1 bit / 512 Bytes 2 bit / 512 Bytes 4 bit / 512 Bytes 8 bit / 512 Bytes 12 bit / 512 Bytes 16 bit / 512 Bytes Reserved Reserved
I/O 7 I/O 6 I/O 5 I/O 4 I/O 3 I/O 2 I/O 1 I/O 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1
Block Size
Redundant Area Size
5th cycle Plane Number
I/O 7 I/O 6 I/O 5 I/O 4 I/O 3 I/O 2 I/O 1 I/O 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 1 0 1
ECC Level
Reserved
www..net
6th cycle
Description 48 nm 41 nm Reserved Reserved Reserved Reserved Reserved Reserved Not Support Support SDR DDR
I/O 7 I/O 6 I/O 5 I/O 4 I/O 3 I/O 2 I/O 1 I/O 0 0 0 0 0 1 1 1 1 0 1 0 1 0 0 0
20
NAND Technology
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
EDO Support NAND Interface Reserved
Rev 0.5 / Jul. 2009
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash
Part Number H27UAG8T2A
VCC 3.3V
Bus Width X8
Manufacture Code ADh
Device Code D5h
3rd 94h
4th 25h
5th 44h
6th 41h
Table 11 : Read ID Data Table
3.15 Reset
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. After a Reset command is issued to, the R/B pin will stay low for tRST as explained in Figure 29. At the end of this time, the command register is ready to process the next command, and the Status Register is cleared to value C0h when WP is high. Refer to Table 6 for device status after reset operation. If the device is already processing a reset, another reset command will not be accepted by the command register .
www..net
Rev 0.5 / Jul. 2009
21
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash
4. OTHER FEATURES
4.1 Data Protection & Power on/off Sequence
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever the power supply (supplies) are below about 2.0V(3.3V device). WP pin provides hardware protection and is recommended to be kept at VIL during power-up and power-down. The Ready/Busy signal shall be valid within 100us since the power supplies have reached the minimum values (as specified on Table 14), and shall return to one within 5msec (max) . The power-up and power-down sequence is shown in Figure 30. During this busy time, the device can accept Read Status Register commands (70h or F1h). At the end of this busy time, the device is ready to accept any other command sequences, The two-step command sequence for program/erase provides additional software protection.
4.2 Ready/ Busy
The Ready/Busy output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is in process, and returns to high state upon completion. The pin is an open-drain driver thereby allowing the R/B outputs of two or more devices to be shorted in a "wired-or" configuration. As the pull-up resistor value is related to tR (R/B) and current drain during busy (Ibusy), an appropriate value can be obtained with the reference chart in Figure 32. Its value can be determined by the guideline detailed in the figure.
4.3 Initialization after power up
After power-up, a reset command must be issued before any other command. As opposed to usual reset commands, this first reset command issues an initialization process on the device. The device stays busy for a maximum of 5ms and consumes a maximum of 40mA current during this process. 70h and F1h (Read Status Register) are the only commands allowed during this initialization process.
www..net
Rev 0.5 / Jul. 2009
22
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash 4.4 Write Protect (WP) handling
Erase and program operations are aborted if WP is driven low during busy time, and kept low for about 100 nsec. Switching WP low during this time will be equivalent to issuing a Reset command (FFh) The contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. The R/B pin will stay low for tRST. At the end of this time, the command register is ready to process the next command, and the Status Register bit IO<6> will be cleared to "1", while IO<7> value will be related to the WP value. Refer to Table 7 for more information on device status. Erase and program operations are enabled or disabled by setting WP to high or low respectively prior to issuing the setup commands (80h or 60h) . The level of WP shall be set tWW nsec prior to raising the WE pin for the set up command, as explained in Figure 35, 36, 37 and 38. Grey area : Switching WP to VIL during any cycle (command, address or data) of a program or erase command sequence will abort the sequence .
www..net
Rev 0.5 / Jul. 2009
23
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash
Parameter Valid Block Number
Symbol NVB
Min 3996
Typ
Max 4096
Unit Blocks
Table 12 : Valid Blocks Number
NOTES : 1. the device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits which cause status failure during program and erase operation. Do not erase or program factory-marked bad blocks. 2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block at the time of shipment. 3. the number of valid blocks is on the basis of single plane operations, and this may be decreased with two plane operations. Symbol Parameter Ambient Operating Temperature (Commercial Temperature Range) TA Ambient Operating Temperature (Extended Temperature Range) Ambient Operating Temperature (Industrial Temperature Range) TBIAS TSTG VIO VCC Temperature Under Bias Storage Temperature Input or Output Voltage Supply Voltage Value 0 to 70 -25 to 85 -40 to 85 -50 to 125 -65 to 150 -0.6 to 4.6 -0.6 to 4.6 Unit ... ... ... ... ... V V
Table 13 : Absolute maximum ratings
NOTES: 1. Stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. 2. Minimum Voltage may undershoot to -2V during transition and for less than 20ns during transitions.
www..net
Rev 0.5 / Jul. 2009
24
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash
VCC = 3.0V (1,2) Min
2.7 -
Parameter
Symbol
Test Condition
FFh COMMAND input after power on tRC=25ns CE=VIL, Iout=0mA
Unit Max
3.6 30 V mA
Typ
3.3 15
Core and I/O Supply voltage Power on reset current
Vcc Icc0
Read Program (Normal) Program (Cache) Erase Stand-by Current (TTL) Stand-by Current (CMOS) Input Leakage Current Output Leakage Current Input High Voltage Input Low Voltage Output High Voltage Level Output Low Voltage Level Output Low Current (R/B)
Icc1
-
15
30
mA
Power on reset current
Icc2
-
15
30
mA
Icc2 Icc3 Icc4 Icc5 ILI ILO VIH Icc0 VOH VOL IOL(R/B) CE=VIH, WP=0V/Vcc CE=Vcc-0.2, WP=0V/Vcc VIN=0 to Vcc max Vout=0 to Vcc max IOH=-400uA IOL=2.1mA VOL=0.4V
Vccx0.8 -0.3 2.4 8
20 15 10 10
40 30 1 50 10 10 Vcc+0.3 0.2xVcc 0.4 -
mA mA mA uA uA uA V V V VC mA
www..net
Table 14 : DC and Operating Characteristics
NOTES : 1. Measurements are performed with a 0.1uF capacitor connected between the Vcc Supply Voltage pin and the Vss Ground pin
Rev 0.5 / Jul. 2009
25
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash
Parameter Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load (1.7 V - 1.95Volt & 2.7V-3.6V)
Value 0V to Vcc 5ns Vcc / 2 1 TTL GATE and CL=50pF
Table 15 : AC Conditions
Symbol CIN CI/O
Parameter Input Capacitance Input/Output Capacitance
Test Condition VIN = 0V VIL = 0V
Min -
Max 10 10
Unit pF pF
Table 16 : Pin Capacitance (TA = 25 F = 1.0 MHz)
MLC VERSION Parameter Random Page read Program (following 10h) Cache Program (following 15h) Multi-Plane Program / Multi-Plane Cache Program / Multi-Plane Copy-Back Program (following 11h) Cache Read / Multi-Plane Cache Read Block Erase / Multi-Plane Block Erase Number of partial Program Cycles in the same page Symbol tR tPROG tCBSYW tDBSY tCBSYR tBERS NOP 800(TBD) 3 3 2.5 Min Typ Max 60 2000 2000(TBD) 5 60 10 1 Unit us us us us us ms cycles
www..net
Table 17 : Program / Read / Erase Characteristics for the MLC version.
Rev 0.5 / Jul. 2009
26
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash
Parameter
CLE setup time(Non-Cache Operation) CLE setup time(Cache Operation) CLE Hold time CE# setup time(Non-Cache Operation) CE# setup time(Cache Operation) CE# hold time WE# pulse width(Non-Cache Operation) WE# pulse width(Cache Operation) ALE setup time(Non-Cache Operation) ALE setup time(Cache Operation) ALE hold time Data setup time(Non-Cache Operation) Data setup time(Cache Operation) Data hold time Write cycle time(Non-Cache Operation) Write cycle time(Cache Operation) WE# high hold time Data transfer from cell to register ALE to RE# delay CLE to RE# delay Ready to RE# low RE# pulse width(Non-Cache Operation) RE# pulse width(Cache Operation) WE# high to busy Read cycle time(Non-Cache Operation) Read cycle time(Cache Operation) RE# access time(Non-Cache Operation)
www..net
Symbol
tCLS tCLS tCLH tCS tCS tCH tWP tWP tALS tALS tALH tDS tDS tDH tWC tWC tWH tR tAR tCLR tRR tRP tRP tWB tRC tRC tREA tREA tRHZ tCHZ tRHOH tRLOH tCOH tREH tCR tWHR
3.3V Min
12 15 5 20 25 5 12 15 12 15 5 12 15 5 25 30 10 60 10 10 20 12 15 100 25 30 20 25 100 50 15 5 15 10 10 80
Max
Unit
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns us ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
RE# access time(Cache Operation) RE# high to output high Z CE# high to output high Z RE# high to output hold RE# low to output hold RE# or CE# high to output hold RE# high hold time CE# low to RE# low WE# high to RE# low
Rev 0.5 / Jul. 2009
27
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash
Parameter
RE# high to WE# low Output high Z to RE# low Address to data loading time Device resetting time (Read/Program/Erase) Write protection time
Symbol
tRHW tIR tADL tRST tWW(2)
3.3V Min
100 0 70 5/10/500(1) 100
Max
Unit
ns ns ns us ns
Table 18 : AC Timing Characteristics
NOTE: (1): If Reset Command(FFh) is written at Ready state, the device goes into Busy for maximum 5us (2): Write protection time to be intended about the following two scenarios: Program / Erase Enable Operation : WP high to WE High. Program / Erase Disable Operation : WP Low to WE High.
www..net
Rev 0.5 / Jul. 2009
28
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash
A31 ~ A0
ADDRESS REGISTER/ COUNTER
PROGRAM ERASE CONTROLLER HV GENERATION
X
ALE CLE WE CE WP RE COMMAND INTERFACE LOGIC
16 Gbit + 469 Mbit NAND Flash MEMORY ARRAY
D E C O D E R
COMMAND REGISTER
PAGE BUFFER Y DECODER
DATA REGISTER BUFFERS
IO
Figure 4 : Block Diagram
www..net
Rev 0.5 / Jul. 2009
29
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash
Figure 5 : Command Latch Cycle
www..net
Figure 6 : Address Latch Cycle
Rev 0.5 / Jul. 2009
30
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash
tCLH
CLE
CE
tCH tWC
ALE
tALS
tWP
WE
tDH
tWP tWH tDS
tDH
tWP tWH tDS
tDH
tDS
I/Ox
DIN 0 Notes: DIN final means 4,224Bytes
DIN 1
DIN final
Figure 7 : Input Data Latch Cycle
tRC
CE RE
tREA tREH tREA tREA
tCHZ tCOH
tRHZ
tRHZ tRHOH
I/Ox
tRR
www..net
Dout
Dout
Dout
R/B
Notes: Transition is measured at +/-200mV from steady state voltage with load. This parameter is sampled and not 100% tested. (tCHZ, tRHZ) tRHOH starts to be valid when frequency is lower than 33MHz. tRLOH is valid when frequency is higher than 33 MHz
Figure 8 : Sequential Out Cycle after Read (CLE = L, WE = H, ALE = L)
Rev 0.5 / Jul. 2009
31
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash
Figure 9 : Sequential Out Cycle after Read (EDO type CLE = L, WE = H, ALE = L)
CLE
tCLR tCLS tCS tCLH
CE
tCH
WE
tWP tCR tWHR tCHZ tCOH
www..net
RE
tDS tDH tIR tREA tRHZ tRHOH Status Output
I/Ox
70h
Figure 10 : Read Status Register
Rev 0.5 / Jul. 2009
32
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash
tCLR
CLE
CE
tWC
WE ALE
tWB tAR tR tRC tRHZ
RE
tRR
I/Ox
00h
Col.Add1 Col.Add2 Row Add1 Row Add2 Row Add3 Column Address Row Address
30h
Dout N
Dout N+
Dout M
R/D
Busy
Figure 11 : Page Read Operation
CLE
CE
WE
tWB
www..net
tCHZ tAR tCOH
ALE
tR
tRC
RE
tRR
I/Ox
00h
Col. Col. Add1 Add2 Column Address
Row Add1
Row Row Add2 Add3 Row Address
30h
Dout N
Dout N+1
Dout N+2
R/B
Busy
Figure 12 : Page Read Operation (Intercepted by CE)
Rev 0.5 / Jul. 2009
33
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash
www..net
Figure 13 : Random Data Output
Rev 0.5 / Jul. 2009
34
www..net
CLE
Rev 0.5 / Jul. 2009
tWC tWB tR
60h 30h Row Address Row. Row. Row. Add1 Add2 Add3 A13 ~ A19 : Valid A20 : Fixed "High" A21 ~ A31 : Valid
CE
tWC
WE
ALE
RE
I/Ox
60h
Row. Row. Row. Add1 Add2 Add3
Row Address
R/B
A13 ~ A19 : Fixed "Low" A20 : Fixed "Low" A21 ~ A31 : Fixed "Low"
Busy 1
CLE
tCLR tCLR
CE
tWC
tWC
WE
tWHR tREA tRC tRHW
tWHR tREA tRC
ALE
RE
05h Column Address A0 ~ A12 : Valid Col. Co2. Add1 Add1 E0h Dout N Dout N+1 00h Col. Co2. Row. Row. Row. Add1 Add1 Add1 Add2 Add3 Column Address Row Address 05h Col. Co2. Add1 Add1 Column Address A0 ~ A12 : Valid A0 ~ A12 : Fixed "Low" A13 ~ A19 : Fixed "Low" A20 : Fixed "High" A21 ~ A31 : Fixed "Low" E0h Dout M Dout M+1
Figure 14 : Multiplane Read Operation with Random Data Output
Row Address
I/Ox
00h
Col. Co2. Row. Row. Row. Add1 Add1 Add1 Add2 Add3
Column Address
R/B
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash
1
A0 ~ A12 : Fixed "Low" A13 ~ A19 : Fixed "Low" A20 : Fixed "Low" A21 ~ A31 : Fixed "Low"
35
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash
Figure 15 : Page Program Operation
www..net
Rev 0.5 / Jul. 2009
36
NOTE: Any command between 11h and 81h is prohibited except, F1h and FFh.
Rev 0.5 / Jul. 2009
tWB tDBSY tWB tPROG tWHR
Col.Add1 Col.Add2 Row Add1 Row Add2 Row Add3
Column Address Page Row Address 1 up to 4224 Byte Data Serial Input Program Command (Dummy)
Multi-Plane Page Program Operation
www..net
CLE
CE
tWC
WE
ALE
RE
Din N 11h Din M
I/Ox
81h
80h
Din Col.Add1 Col.Add2 Row Add1 Row Add2 Row Add3 N
Din M Serial Input
10h Program Command (True)
F1h
I/O
Serial Data Input Command
R/B
tDBSY : 1us (Typ.) 2us (Max.) I/O 1 = 0 Successful Program in plane 0 I/O 1 = 1 Error in plane 0 I/O 2 = 0 Successful Program in plane 1 I/O 2 = 1 Error in plane1
Ex.) Two-Plane Page Program
Figure 16 : Multiplane Page Program
R/B I/O0~7
80h
Address & Data Input 11h
tDBSY
tPROG
81h
Address & Data Input
10h
F1h
Col Add 1,2 & Row Add 1,2 3 4224 Byte Data A0 ~ A12 Valid A13 ~ A19 Fixed `Low' A20 Fixed `Low' A21 ~ A31 Fixed `Low'
Note
Col Add 1,2 & Row Add 1,2 3 4224 Byte Data A0 ~ A12 Valid A13 ~ A19 Valid A20 Fixed `High' A21 ~ A31 Valid
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash
Note: Any command between 11h and 81h is prohibted except, F1h and FFh
37
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash
www..net
Figure 17 : Random Data Input
Rev 0.5 / Jul. 2009
38
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash
Figure 18 : Block Erase
www..net
Rev 0.5 / Jul. 2009
39
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash
CLE
CE
tWC tWC
WE
tWB tBERS tWHR
ALE
RE
I/Ox
60h
Row Add1 Row Add2 Row Add3
60h
Row Add1
Row Add2
Row Add3
D0h
F1h
I/O
Row Address
Row Address Busy
R/B
Block Erase Setup Command1 Block Erase Setup Command2 Erase Confirm Command
Read Status Command I/O 1 = 0 Successful Program in plane 0 I/O 1 = 1 Error in plane 0 I/O 2 = 0 Successful Program in plane 1 I/O 2 = 1 Error in plane1
Ex.) Address Restriction for Two-Plane Block Erase Operation R/B I/O0~7
tBERS
60h
Address
60h
Address
D0h
70h
Row Add1,2,3 A13 ~ A19 : Fixed `Low' A20 : Fixed `Low' A21 ~ A31 : Fixed `Low'
Row Add1,2,3 A13 ~ A19 : Fixed `Low' A20 : Fixed `High' A21 ~ A31 : Valid
www..net
Figure 19 : Multiplane Block Erase
Rev 0.5 / Jul. 2009
40
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash
www..net
Figure 20 : Copy Back Program Operation
....
Rev 0.5 / Jul. 2009
41
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash
www..net
Figure 21 : Copy Back with Random Data Input....
......
Rev 0.5 / Jul. 2009
42
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash
R/B
tR
I/Ox
60h
Address (3 Cycle) Row Add. 1,2,3 A13 ~ A19 : Fixed "Low" A20 : Fixed "Low" A21 ~ A31 : Fixed "Low"
60h
Address (3 Cycle) Row Add. 1,2,3 A13 ~ A19 : Valid A20 : Fixed "High" A21 ~ A31 : Valid
35h
1
R/B I/Ox
00h Address (5 Cycle) 05h Address (2 Cycle) Col. Add 1,2 A0 ~ A12 : Valid 2 E0h Data Output
Col. Add 1,2 & Row Add. 1,2,3 1 A0 ~ A12 : Fixed "Low" A13 ~ A19 : Fixed "Low" A20 : Fixed "Low" A21 ~ A31 : Fixed "Low"
R/B I/Ox
2 00h Address (5 Cycle) 05h Address (2 Cycle) Col. Add 1,2 A0 ~ A12 : Valid E0h Data Output 3
Col. Add 1,2 & Row Add. 1,2,3 A0 ~ A12 : Fixed "Low" A13 ~ A19 : Fixed "Low" A20 : Fixed "High" A21 ~ A31 : Fixed "Low"
tDBSY
tPROG
R/B
I/Ox
3
www..net
85h
Add. (5Cycles)
11h
81h
Add. (5Cycles)
10h
F1h
I/O
Col. Add 1,2 & Row Add. 1,2,3 Destination Address A0 ~ A12 : Fixed "Low" A13 ~ A19 : Fixed "Low" A20 : Fixed "Low" A21 ~ A31 : Fixed "Low"
Col. Add 1,2 & Row Add. 1,2,3 Destination Address A0 ~ A12 : Fixed "Low" A13 ~ A19 : Valid A20 : Fixed "High" A21 ~ A31 : Valid
I/O 1 = 0 Successful Program in plane 0 I/O 1 = 1 Error in plane 0 I/O 2 = 0 Successful Program in plane 1 I/O 2 = 1 Error in plane1
Note : 1. Copy back operation is allowed only within the same memory plane 2. Any command between 11h and 81h is prohibited except 70h, F1h and FFh
Figure 22 : Multiplane Copy Back
......
Rev 0.5 / Jul. 2009
43
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash
R/B
tR
I/Ox
60h
Address (3 Cycle) Row Add. 1,2,3 A13 ~ A19 : Fixed "Low" A20 : Fixed "Low" A21 ~ A31 : Fixed "Low"
60h
Address (3 Cycle) Row Add. 1,2,3 A13 ~ A19 : Valid A20 : Fixed "High" A21 ~ A31 : Valid
35h
1
R/B I/Ox
00h Address (5 Cycle) 05h Address (2 Cycle) Col. Add 1,2 A0 ~ A12 : Valid 2 E0h Data Output
Col. Add 1,2 & Row Add. 1,2,3 1 A0 ~ A12 : Fixed "Low" A13 ~ A19 : Fixed "Low" A20 : Fixed "Low" A21 ~ A31 : Fixed "Low"
R/B I/Ox
2 00h Address (5 Cycle) 05h Address (2 Cycle) Col. Add 1,2 A0 ~ A12 : Valid E0h Data Output 3
Col. Add 1,2 & Row Add. 1,2,3 A0 ~ A12 : Fixed "Low" A13 ~ A19 : Fixed "Low" A20 : Fixed "High" A21 ~ A31 : Fixed "Low"
tDBSY
R/B
I/Ox
3
85h
Address (5 Cycles)
Data
85h
Address (2 Cycles)
Data
11h 4
Col. Add 1,2 & Row Add. 1,2,3 Destination Address A0 ~ A12 : Valid A13 ~ A19 : Fixed "Low" A20 : Fixed "Low" A21 ~ A31 : Fixed "Low"
www..net
Col. Add 1,2
tPROG
R/B I/Ox
4 81h
Address (5 Cycles)
Data
85h
Address (2 Cycles)
Data
10h
Col. Add 1,2 & Row Add. 1,2,3 Destination Address A0 ~ A12 : Valid A13 ~ A19 : Valid A20 : Fixed "High" A21 ~ A31 : Valid
Col. Add 1,2
NOTE
1. Copy Back Program operation is allowed only within the same memory plane. 2. Any Command between 11h and 81h is prohibited except 70h FFh and F1h
Figure 23 : Multiplane Copy Back with Random Data Input
Rev 0.5 / Jul. 2009 44
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash
www..net
Figure 24 : Read Operation with Cache
Rev 0.5 / Jul. 2009
45
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash
tR R/B Command input 60h Address input
A13 ~ A19 : Fixed "Low" A20 : Fixed "Low" A21 ~ A31 : Fixed "Low"
60h
Address input
A13 ~ A19 : Valid A20 : Fixed "High" A21 ~ A31 : Valid
30h 1
tRBSY R/B Command input 31h 1 00h Address input
A0 ~ A12 : Fixed "Low" A13 ~ A19 : Fixed "Low" A20 : Fixed "Low" A21 ~ A31 : Fixed "Low"
05h
Address input
A0 ~ A12 : Valid
E0h
Data output 2
R/B Command input 00h 2 Address input 05h Address input
A0 ~ A12 : Valid
E0h
Data output 3
A0 ~ A12 : Fixed "Low" A13 ~ A19 : Fixed "Low" A20 : Fixed "High" A21 ~ A31 : Fixed "Low"
Return to 1 Repeat a max of 63 times
tRBSY R/B Command input 3Fh 3
www..net
00h
Address input
A0 ~ A12 : Fixed "Low" A13 ~ A19 : Fixed "Low" A20 : Fixed "Low" A21 ~ A31 : Fixed "Low"
05h
Address input
A0 ~ A12 : Valid
E0h
Data output 4
R/B Command input 00h 4 Address input 05h Address input
A0 ~ A12 : Valid
E0h
Data output
A0 ~ A12 : Fixed "Low" A13 ~ A19 : Fixed "Low" A20 : Fixed "High" A21 ~ A31 : Fixed "Low"
Figure 25 : Multi Plane Read Operation with Cache
Rev 0.5 / Jul. 2009
46
www..net
Rev 0.5 / Jul. 2009
tWB tCBSY tWB tPROG
Col. Add1 Col. Add2 Din N Row Add1 Row Add2 Row Add3
CLE
CE
tWC
WE
ALE
RE
Din M 15h 80h Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3 Din N Din M 10h 70h I/O
I/Ox
Serial Input Program Command (Dummy)
80h
Serial Data Column Address Row Address Input Command
Program Confirm Command (True)
R/B
Max. 63 times repeatable tCBSY: max. 700us
Last Page Input & Program
Ex.) Cache Program
Figure 26 : Program Operation with Cache
R/B I/Ox
Col Add 1,2 & Row Add 1,2 Data
80h Address & Data Input 15h 80h Address & Data Input
tCBSY
tCBSY
tCBSY
tPROG
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash
15h
80h
Address & Data Input
15h
80h
Address & Data Input
10h
70h
47
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash
Command Input 80h Address Input A13 ~ A19 : Fixed "Low" A20 : Fixed "Low" A21 ~ A31 : Fixed "Low" Data Input 11h 81h Address Input A13 ~ A19 : Valid A20 : Fixed "High" A21 ~ A31 : Valid Data Input 15h
RY/RY 1
Return to 1 repeat a max of 191 times
Command Input 80h Address Input A13 ~ A19 : Fixed "Low" A20 : Fixed "Low" A21 ~ A31 : Fixed "Low" Data Input 11h 80h Address Input A13 ~ A19 : Valid A20 : Fixed "High" A21 ~ A31 : Valid Data Input 10h
RY/RY 1
CLE
CE
tWC tWC
WE
tWB
ALE
RE
Page N Page N+1 Row Add3 Din N Din N 11h 81h Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3 Din N Din N 15h 80h Col. Add1 Col. Add2 Row Add1 Row Add2
I/Ox
Column Address
Row Address
Column Address
Row Address
R/B
tDBSY tCBSY
1
CLE
CE
tWC
www..net
tWC
WE
ALE
RE
Page N Page N+1 Row Add3 Din N Din N 11h 81h Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3 Din N Din N 10h 71h I/OQ 80h Col. Add1 Col. Add2 Row Add1 Row Add2
I/Ox
Column Address
Row Address
Column Address
Row Address
R/B 1
tDBSY tPROG
Figure 27 : Multi Plane Cache Program
Rev 0.5 / Jul. 2009
48
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash
CLE CE WE
tAR
ALE RE
tREA
I/O x
90h
Read ID Command
00h
Address 1 cycle
ADh
D5h
94h
3rd Cycle
25h
4th Cycle
44h
5th Cycle
41h
6th Cycle
Maker Code Device Code
Figure 28 : Read ID Operation
www..net
Figure 29 : Reset Operation
Rev 0.5 / Jul. 2009
49
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash
Figure 30 : Power on and Data Protection Timing
www..net
Power on
FF Reset
Figure 31 : Power on Reset
Rev 0.5 / Jul. 2009
50
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash
Vcc
Rp
ibusy
Ready Vcc
R/B open drain output
VOL : 0.8V, VOH : 2.0V VOL tf Busy tr
VOH
GND Device Fig. Rp vs tr, tf & Rp vs ibusy
@ Vcc = 3.3 V, Ta = 25 C, CL = 100 pF
3.3
381
tr, tf [s]
200n 100n
96 4.2
189
1.1 0.825
2m 1m
tf
4.2
4.2
4.2
1k
2k
3k Rp (ohm)
4k
Rp value guidence
Rp (min) = Vcc (Max.) - VOL (Max.) IOL +
L
=
3.2V
L
where IL is the sum of the input currnts of all devices tied to the R/B pin.
www..net
Rp(max) is determined by maximum permissible limit of tr
Figure 32 : Ready / Busy Pin Electrical Specifications
Rev 0.5 / Jul. 2009
ibusy [A]
51
300n
ibusy
1.65
290
3m
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash
Bad Block Management
Devices with Bad Blocks have the same quality level and the same AC and DC characteristics as devices where all the blocks are valid. A Bad Block does not affect the performance of valid blocks because it is isolated from the bit line and common source line by a select transistor. The devices are supplied with all the locations inside valid blocks erased(FFh). The Bad Block Information is written prior to shipping. Any block where the 1st Byte in the spare area of the Last and (Last2)th page (if the last page is Bad) does not contain FFh is a Bad Block. The Bad Block Information must be read before any erase is attempted as the Bad Block Information may be erased. For the system to be able to recognize the Bad Blocks based on the original information it is recommended to create a Bad Block table following the flowchart shown in Figure 34. The 1st block, which is placed on 00h block address is guaranteed to be a valid block.
www..net
Figure 33 : Bad Block Management Flowchart
NOTE : 1. Make sure that FFh at the column address 4096 of the last page and last - 2th page.
Rev 0.5 / Jul. 2009
52
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash Bad Block Replacement
Over the lifetime of the device additional Bad Blocks may develop. In this case the block has to be replaced by copying the data to a valid block. These additional Bad Blocks can be identified as attempts to program or erase them will give errors in the Status Register. The failure of a page program operation does not affect the data in other pages in the same block, the block can be replaced by re-programming the current data and copying the rest of the replaced block to an available valid block. Refer to Table 19 and Figure 34 for the recommended procedure to follow if an error occurs during an operation.
Operation Erase Program Read
Recommended Procedure Block Replacement Block Replacement ECC (with 12 bit/512byte)
Table 19 : Block Failure
Block A
Block B
Data
(2)
Data
n th page
Failure (1) (3) FFh FFh
www..net
Buffer memory of the controller
Figure 34 : Bad Block Replacement
NOTE : 1. An error occurs on the Block A during program or erase operation. 2. Data in Block A is copied to same location in Block B which is valid block. 3. Nth data of block A which is in controller buffer memory is copied into nth page of Block B 4. Bad block table should be updated to prevent from erasing or programming Block A
Rev 0.5 / Jul. 2009
53
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash Write Protect Operation
The Erase and Program Operations are automatically reset when WP goes Low (tWW = 100ns, min). The operations are enabled and disabled as follows (Figure 35~38)
WE t WW I/Ox 80h 10h
WE
t WW
I/Ox
80h
10h
WP
WP
R/B
R/B
Figure 35 : Enable Programming
Figure 36 : Disable Programming
WE
t WW
WE
t WW
D0h
I/Ox
60h
I/Ox
60h
D0h
WP
WP
www..net
R/B
R/B
Figure 37 : Enable Erasing
Figure 38 : Disable Erasing
Rev 0.5 / Jul. 2009
54
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash Paied Page Address Information
Paired Page Address Group A 00h 02h 06h 0Ah 0Eh 12h 16h 1Ah 1Eh 22h 26h 2Ah 2Eh 32h 36h 3Ah 3Eh 42h 46h 4Ah 4Eh 52h 56h 5Ah 5Eh 62h
www..net
Paired Page Address Group B 04h 08h 0Ch 10h 14h 18h 1Ch 20h 24h 28h 2Ch 30h 34h 38h 3Ch 40h 44h 48h 4Ch 50h 54h 58h 5Ch 60h 64h 68h 6Ch 70h 74h 78h 7Ch 7Eh Group A 01h 03h 07h 0Bh 0Fh 13h 17h 1Bh 1Fh 23h 27h 2Bh 2Fh 33h 37h 3Bh 3Fh 43h 47h 4Bh 4Fh 53h 57h 5Bh 5Fh 63h 67h 6Bh 6Fh 73h 77h 7Bh Group B 05h 09h 0Dh 11h 15h 19h 1Dh 21h 25h 29h 2Dh 31h 35h 39h 3Dh 41h 45h 49h 4Dh 51h 55h 59h 5Dh 61h 65h 69h 6Dh 71h 75h 79h 7Dh 7Fh
66h 6Ah 6Eh 72h 76h 7Ah
NOTE: When program operation is abnormally aborted (ex. power-down, reset), not only page data under program but also paired page data may be damaged.
Rev 0.5 / Jul. 2009
55
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash
Figure 39 : 48-TSOP1 - 48-lead Plastic Thin Small Outline, 12 x 20mm, Package Outline
Symbol A A1 A2 B C CP D E E1 e L alpha
www..net
millimeters
Min Typ Max 1.200 0.050 0.980 0.170 0.100 0.150 1.030 0.250 0.200 0.100 11.910 19.900 18.300 12.000 20.000 18.400 0.500 0.500 0 0.680 5 12.120 20.100 18.500
Table 20 : 48-TSOP1 - 48-lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data
Rev 0.5 / Jul. 2009
56
1 Preliminary H27UAG8T2A Series 16 Gbit (2048 M x 8 bit) NAND Flash
MARKING INFORMATION - TSOP1
M a rk in g E x a m p le
K H 2 7 U A G 8 T 2 A x x -
O x
R x
Y
W
W
x
x
- h y n ix - KOR - H 2 7 U 1 G 8 F 2 B x x -x x H : H yn ix 2 7 : N A N D Fla sh U : P o w e r S u p p ly A G : D e n sity 8 : B it O rg an iza tion T : C la ssification 2 : M o de A : V e rsion x : P a cka g e T ype x : P a cka g e M ate rial x : B ad B lo ck
www..net
: H yn ix S ym b o l : O rigin C o u n try : P a rt N u m be r
: U (2 .7 V ~ 3 .6 V ) : 1 6 G bit : 8 (x8 ) : M u lti Leve l C e ll+ S in g le D ie + Large B lo ck : 2 (1 n C E & 1 R /n B ; S e q u e n tia l R ow R e a d D isa b le ) : 2 n d G e n era tion : T (4 8 -T S O P 1 ) : B la n k(N o rm a l), R (Le ad & H a lo ge n Free ) : B (In clu d ed B ad B lo ck ), S (1 ~ 5 B a d B lock ), P (A ll G oo d B lock) : C (0 ~ 7 0 ), I(-4 0 ~ 8 5 )
x : O p e ra tin g T e m pe ra tu re
- Y : Y e ar (ex: 8= year 2 0 0 8 , 9= year 20 09 ) - w w : W o rk W e ek (e x: 1 2 = w o rk w e ek 1 2 ) - x x : P roce ss C od e N o te - C a p ita l L e tte r - S m a ll L e tte r : Fixed Item : N o n -fixe d Item
Rev 0.5 / Jul. 2009
57

▲Up To Search▲

Price & Availability of H27UAG8T2A

	To Download H27UAG8T2A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .